1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
In recent years, an operating frequency of a semiconductor integrated circuit device is extremely increasing. When the semiconductor integrated circuit device is operated at a high frequency, a fluctuation in power supply voltage such as temporary current spike easily occurs. In an integrated circuit including a plurality of circuits, noise is propagated between circuits, and the circuit may erroneously operate. In a conventional art, a technique in which a decoupling capacitor is connected in parallel to a power supply in order to suppress a fluctuation in power supply voltage is known. In this manner, a power supply noise can be reduced to make it possible to suppress the fluctuation in power supply voltage, and a semiconductor integrated circuit device can be prevented from being erroneously operated by power supply noise and the fluctuation in power supply voltage. In order to achieve the object, the decoupling capacitor which is arranged due to the fluctuation in power supply voltage must have a capacitance of about several ten nano-farads with respect to one chip or package. However, when the decoupling capacitor as described above is arranged, a mounting area increases, and a degree of integration disadvantageously reduces.
In Japanese Patent Application Laid-Open No. 2001-36015, a technique is described in which; a bottom N well is formed on a p-type silicon substrate, an N well and a P well which are adjacent to each other are formed thereon, a voltage Vcc is applied to an N-diffusion region, a ground voltage GND is applied to a P-diffusion region, and a capacitor between the power supply voltage Vcc and the ground voltage Vss is formed on the contact surface between the N well and P well, and between the P well and the bottom N well. In this manner, problems such as necessity of a region and an interconnect required for a capacitor and a reduction in effective area in which a device can be arranged can be solved.
In Japanese Patent Application Laid-Open No. 2004-146613, a configuration is described in which a rear surface of a substrate is connected to a power supply terminal, and a pn junction is formed between the substrate and an inverse-conductivity-type epitaxial layer formed thereon to form a capacitor. In this manner, a semiconductor integrated circuit device which does not need a special arrangement region for arranging a decoupling capacitor, and easily manufactured is provided.
However, the present inventors have found that, in the configuration described in Japanese Patent Application Laid-Open No. 2001-36015, frequency characteristics of the decoupling capacitor are deteriorated when a well size is not appropriately set in formation of the decoupling capacitor. FIG. 7 is a sectional view showing a configuration in which an N well 208 is formed in a P well 206. In this configuration, a capacitor component is formed on a contact surface between a bottom surface of the N well 208 and the P well 206, and the capacitor component functions as a decoupling capacitor. However, when the N well 208 increases in width, although the capacitor component at a circumference portion of the N well 208 is applicable to a high frequency, a high resistance is applied to the capacitor component at a central portion of the N well 208. For this reason, when a frequency applied to the semiconductor device increases, with reference to an impedance of a decoupling capacitor configured by the N well 208 and the P well 206, a parasitic resistance caused by a resistance of the N well 208 cannot be neglected, and the decoupling capacitor does not function as a capacitor.